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9-3-2 p-i-n¥ú¹q¤G·¥Åé (p-i-n Photodiode) 9-3-3 ¥ú¹q¹q´¹Åé (Phototransistor) 9-4 ¤Ó¶§¹q¦À(Solar Cell) 9-4-1 PERL¤Ó¶§¹q¦À (PERL Solar Cell) 9-4-2 ¦ê¯Å¤Ó¶§¹q¦À (Tandem Solar Cell) 9-4-3 «D´¹¤Ó¶§¹q¦À (Amorphous Solar Cell) 9-4-4 »E¥ú (Optical Concentration) ²ßÃD ²Ä¤T½g ¿nÅé¹q¸ô»sµ{»P³]³Æ ²Ä10³¹ ª¿´¹´Î¤§¥Íªø 10-1 ì®Æ°t»s (Starting Materials) 10-2 ª¿´¹´Î¥Íªø (Silicon Ingot Growth) 10-3 ´¹Åé¥Íªø®ÉºUÂø½è¤§¤À§G (Dopants Distribution in Crystal Growth) 10-4 ´¹Åé¯Ê³´¡]Crystal Defects¡^ ²ßÃD ²Ä11³¹ ª¿´¹¶ê¤§»s§@ 11-1 ´¹Åé¤è¦V¡]Crystal Orientation¡^ 11-2 ´¹¤ù¤è¦V¡B¤Á³Î©M©ß¥ú (Orientation¡BSawing and Polishing) 11-3 ¤Q¤G¦T´¹¶ê®Ä¯q¤ÀªR¡]Benefit Analysis of 12 Inch wafer¡^ ²ßÃD ²Ä12³¹ ¤Æ¦Xª«¥b¾ÉÅé´¹´Î¥Íªø 12-1 ¯~¤ÆñS´¹´Î¥Íªø (Gallium Arsenide Ingot Growth) 12-2 ¥Íªø (Gallium Nitride Ingot Growth) 12-3 ºÒ¤Æª¿´¹´Î¥Íªø (Silicon Carbide Ingot Growth) 12-3-1 °ª·Åª«²z®ð¬Û¨I¿nªk (HTPVD) 12-3-2 °ª·Å¤Æ¾Ç®ð¬Û¨I¿nªk (HTCVD) ²ßÃD ²Ä13³¹ ª¿½U´¹¥Íªø 13-1 ½U´¹½¤¡]Epitaxial Layer¡^ 13-2 ª¿½U´¹¥Íªø¡]Silicon Epiatxy¡^ 13-3 ª¿½U´¹½¤¥Íªøµ{§Ç¡]Growth Process of Si Epitaxial Layer¡^ ²ßÃD ²Ä14³¹ ª¿½U´¹¨t²Î 14-1 ª¿½U´¹¨t²Î¡]Epitaxy Systems¡^ 14-2 ª¿½U´¹¥Íªø¨t²Î¤§µû¦ô¡]Evaluation of Epitaxial Systems¡^ ²ßÃD ²Ä15³¹ ¤Æ¦Xª«¥b¾ÉÅé½U´¹¦¨ªø 15-1 ¯~¤ÆñS½U´¹¦¨ªø¡]GaAs Epitaxy¡^ 15-1-1 ¯~¤ÆñS²B¤Æª«®ð¬Û½U´¹ (Hydride Vapor Phase Epitaxy-HVPE) 15-1-2 ¯~¤ÆñS¦³¾÷ª÷ÄݤƾǮð¬Û½U´¹ 15-2 ´á¤ÆñS½U´¹¥Íªø¡]GaN Epitaxy¡^ 15-2-1 ´á¤ÆñS²B¤Æª«®ð¬Û½U´¹ (Hydride Vapor Phase Epitaxy-HVPE) 15-2-2 ´á¤ÆñS¦³¾÷ª÷ÄݤƾǮð¬Û½U´¹ 15-3 ºÒ¤Æª¿½U´¹¥Íªø¡]SiC Epitaxy¡^ ²ßÃD ²Ä16³¹ ª¿®ñ¤Æ½¤¥Íªø 16-1 ¼ö®ñ¤ÆÄl¡]Thermal Oxidation Furnace¡^ 16-2 ª¿®ñ¤Æµ{§Ç¡]Oxidation Process¡^ 16-3 °®Àã®ñ¤Æ»P½¤«p¡]Dry and Wet Oxidation and Thickness¡^ 16-4 ª¿®ñ¤Æ½¤«p«×µû¦ô¡]Oxide Evaluation¡^ 16-5 ¼ö®ñ¤Æ®ÉºUÂøì¤l¤§«¦æ¤À§G (Redistribution of Dopant Atoms During Thermal Oxidation¡^ ²ßÃD ²Ä17³¹ ª¿®ñ¤Æ½¤¥Íªø¾÷¨î 17-1 ¤G®ñ¤Æª¿»P®ñ¤Æ¡]Silicon Dioxide and Oxidation¡^ 17-2 ®ñ¤Æ¾÷¨î¡]Oxidation Mechanism¡^ 17-3 ¶WÁ¡®ñ¤Æ¼h¡]Ultra-Thin Oxide¡^ 17-4 ®ñ¤Æ½¤«~½èµû¦ô¡]Oxide Quality Evaluation¡^ 17-5 ®ñ¤Æ½¤«~½è§ï¶i¤èªk¡]Improvement of Oxide Quality¡^ ²ßÃD ²Ä18³¹ ºUÂø½è¤§ÂX´²´Ó¤J 18-1 ÂX´²·§©À (Concept of Diffusion) 18-2 ÂX´²¹Lµ{ (Diffusion Process) 18-3 ÂX´²¤§¤À§G¦±½u (Distribution of Diffusion) ²ßÃD ²Ä19³¹ ºUÂø½è¤§Â÷¤l§G´Ó 19-1 Â÷¤l§G´Ó (Ion Implantation) 19-2 °h¤õ (Annealing) 19-3 Â÷¤l§G´Ó¦bCMOS¿nÅé¹q¸ô»sµ{¤WªºÀ³¥Î(Ion Implantation in CMOS IC Fabrication) 19-3-1 ½Õ¾ã¹q´¹ÅéÁ{¬É¹qÀ£ (Adjustment of Transistor Threshold Voltage) 19-3-2 §Î¦¨N¤ÎP«¬¤«°Ï (Formation of N and P Wells) 19-3-3 ¹q´¹Å骺¹jÂ÷ (Isolation) 19-3-4 §Î¦¨¹q´¹Å骺·½·¥»P¨V·¥ (Formation of Source and Drain) 19-3-5 §Î¦¨§CºUÂø¿@«×ªº¨V·¥ (Lightly-Doped Drain Formation) 19-3-6 ºUÂø½Æ´¹ª¿ (Poly-silicon Doping) 19-3-7 SOI´¹¶ê¥Íªø³Æ»s (Preparation of SOI Wafer) 19-4 Â÷¤l§G´Ó»sµ{¹ê°È (Practices of Ion Implantation) 19-4-1 ´¹¶ê§N«o (Wafer Cooling) 19-4-2 ¥úªý°ÝÃD (Resist Problems) 19-4-3 ¹q²ü¤¤©M (Charge Neutralization) 19-4-4 ·L¹Ð»P¦Ã¬V (Dust and Contamination) ²ßÃD ²Ä20³¹ ·L¼v§Þ³N 20-1 ·L¼v»k¨è³N (Lithography) 20-2 ¥ú¸n¤§»s§@ (Fabrication of Mask) 20-3 ¥ú·L¼v³N (photolithography) 20-4 ¥ú¸ÑªR¼W±j·L¼v³N (Resolution Enhancement Techniques) 20-5 ·L¼v³N¤§¥ú·½ (Photolithographic sources) 20-5-1 ¹q¤l§ô·L¼vÃn¥ú¨t²Î (Electron Beam Lithography) 20-5-2 ·¥²`µµ¥~¥ú·L¼vÃn¥ú¨t²Î (Extreme Ultraviolet Lithography) ²ßÃD ²Ä21³¹ »k¨è§Þ³N 21-1 Àã»k¨è (Wet Etching) 21-1-1 ª¿Àã»k¨è (Si Wet Etching) 21-1-2 ¤Æ¦Xª«¥b¾ÉÅéÀã»k¨è (Compound Semiconductor Wet Etching) 21-2 °®»k¨è (Dry Etching) 21-2-1 ¹q®e½¢¦X¦¡¹q¼ß»k¨è¾÷ (Capacitively Coupled Plasma etcher) 21-2-2 ¬¡¤ÆÂ÷¤l»k¨è¾÷ (RIE-Reactive Ion Etcher) 21-2-3 ÃäÀð¾÷¨î»²§U«Dµ¥¦V©Ê»k¨è (Anisotropic Etching Assisted by Sidewall Mechanism) 21-2-4 ¹q·P½¢¦X¦¡¹q¼ß»k¨è¾÷ (Inductively Coupled Plasma Etcher-ICP) 21-2-5 »·ºÝ¹q¼ß»k¨è¾÷ (Remote Plasma Etcher) 21-2-6 ¤Æ¦Xª«¥b¾ÉÅé°®»k¨è (Compound Semiconductor Dry Etching) 21-2-7 ì¤l¼h»k¨è§Þ³N (Atomic Layer Etching) 21-2-8 »EµJÂ÷¤l§ô (Focused Ion Beam, FIB) 21-2-9 ¤Æ¾Ç¾÷±ñ©ß¥ú (Chemical-mechanical polishing, CMP) ²ßÃD ²Ä22³¹ ¤Æ¾Ç®ð¬Û¨I¿n 22-1 ¤Æ¾Ç®ð¬Û¨I¿n·§©À (Introduction of CVD) 22-2 ¤Æ¾Ç®ð¬Û¨I¿n¬yµ{ (CVD Procedures) 22-3 §CÀ£¤Æ¾Ç®ð¬Û¨I¿n (Low Pressure CVD - LPCVD) 22-4 ¹q¼ß¤Æ¾Ç®ð¬Û¨I¿n (Plasma CVD - PCVD) 22-5 ¥ú·Ó¤Æ¾Ç®ð¬Û¨I¿n (Photo-CVD) 22-6 ì¤l¼h¨I¿n (Atomic Layer Deposition) 22-7 ²G¬Û¨I¿nªk (Liquid Phase Deposition) ²ßÃD ²Ä23³¹ ª÷ÄݱµÄ²»P¨I¿n 23-1 ª÷ÄݤƤ§n¨D (Metallization Requirements) 23-2 ¯uªÅ¨I¿n (Vacuum Deposition) 23-3 ¨I¿n§Þ³N (Deposition Techniques) 23-4 ¯uªÅ¨I¿nµ{§Ç (Vacuum Deposition Procedure) 23-5 ¦Xª÷/°h¤õ (Alloy/Annealing) 23-6 ª÷Äݪ¿¤Æª« (Silicide) 23-6-1 ºUÂø¦h´¹ª¿ (Doped Polysilicon) 23-6-2 ª÷Äݪ¿¤Æª«»P¦h´¹ª¿¤Æª« (Silicide and Polycide) 23-7 »É»sµ{§Þ³N (Copper Processes) ²ßÃD ²Ä24³¹ ¿nÅé¹q¸ô«Ê¸Ë 24-1 ¿nÅé¹q¸ô«Ê¸Ë (IC Package) 24-1-1 ¿nÅé¹q¸ô¤¤¥b¾ÉÅ餸¥ó¥¢®Äªº¥D¦] (IC Failure Analysis) 24-1-2 «Ê¸Ëªº¥\¯à (Function of Packaging) 24-1-3 ¿nÅé¹q¸ô«Ê¸Ë§÷®Æªºn¨D (Material Requirements) 24-2 «Ê¸Ë¤ÀÃþ (Classification) 24-3 «Ê¸Ë¬yµ{ (Packaging Flow Chart) 24-3-1 I±¬ã¿i (Back-Side Grinding) 24-3-2 ´¹¤ù´z¿ï (Chip Sorting) 24-3-3 ´¹¶ê¤Á³Î ( Sawing) 24-3-4 ¾Z´¹ (Die Attaching) 24-3-5 ¾Z½u (Wire Bonding) 24-3-6 «Ê½¦ (Molding) 24-3-7 ¹qÁá (Solder Plating) 24-3-8 Ås¸}¦¨§Î (Forming) 24-3-9 ³Ì«á´ú¸Õ (Final Testing) 24-3-10 ¥´¥] (Packing) 24-4 ¤Tºû«Ê¸Ë (3 Dimensional Package) ²ßÃD ²Ä¥|½g ¿nÅé¹q¸ô¬G»Ù»PÀË´ú ²Ä25³¹ ¥i¾a«×»P¥\¯à©ÊÀË´ú 25-1 ¥i¾a«×°ò¥»·§©À (Basic Idea of Reliability) 25-2 ¥i¾a«×ÀË´ú (Reliability Testing) 25-3 ¬G»Ù¼Ò«¬ (Failure Models) 25-3-1 ¬G»Ù¥§¡¹Ø©R (Mean-time-to-failure¡AMTTF) 25-3-2 ¥§¡¬G»Ù¶¡¹j®É¶¡ (Mean-Time-Between-Failure, MTBF) 25-4 ¹qºÏ¤zÂZ (EMI) 25-5 ÀR¹q®ÄÀ³ (ESD) 25-6 ¥\¯à©ÊÀË´ú (Function Testing) 25-6-1 ¥iÀË´ú³]p (Design for Testability) 25-6-2 ¤º«Ø¦¡¦Û§ÚÀË´ú (Built-in Self-Test, BIST) 25-6-3 ¥i×Å@ (Repairable) ²ßÃD ²Ä26³¹ §÷®Æ¯S©ÊÀË´ú 26-1 ªí±§ÎºA¤ÀªR»ö¾¹ (Surface Morphology Analysis Instruments) 26-1-1 ¥ú¾ÇÅã·LÃè (Optical Microscope-OM) 26-1-2 ±½´y¦¡¹q¤lÅã·LÃè (Scanning Electron Microscopy- SEM) 26-1-3 ì¤l¤OÅã·LÃè (Atomic Force Microscopy-AFM) 26-2 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